CS302 Final Term Solved MCQS By Moaz
Question No: 1 ( Marks: 1 )  Please choose
one
A
8bit serial in / parallel out shift register contains the value “8”, _____
clock signal(s) will be required to shift the value completely out of the
register.
► 1
► 2
► 4
► 8 (Page 356)
Question
No: 2 ( Marks: 1 )  Please choose one
In a sequential circuit the next state is
determined by ________ and _______
► State variable,
current state
► Current state,
flipflop output
► Current state and
external input (Page 318)
► Input and clock signal
applied
Question
No: 3 ( Marks: 1 )  Please choose one
The
divideby60 counter in digital clock is implemented by using two cascading
counters:
► Mod6, Mod10 (Page
299)
► Mod50, Mod10
► Mod10, Mod50
► Mod50, Mod6
Question
No: 4 ( Marks: 1 )  Please choose one
In
NOR gate based SR latch if both S and R inputs are set to logic 0, the
previous output state is maintained.
► True (Page 221)
► False

Question
No: 5 ( Marks: 1 )  Please choose one
The
minimum time for which the input signal has to be maintained at the input of
flipflop is called ______ of the flipflop.
► Setup time
► Hold time (Page 242)
► Pulse Interval time
► Pulse Stability time
(PST)

Question
No: 7 ( Marks: 1 )  Please choose one
____________
is said to occur when multiple internal variables change due to change in one
input variable
► Clock Skew
► Race condition (Page
267)
► Hold delay
► Hold and Wait

Question
No: 8 ( Marks: 1 )  Please choose one The_____________ input overrides the
________ input ► Asynchronous,
synchronous (Page 369)
► Synchronous,
asynchronous
► Preset input (PRE),
Clear input (CLR)
► Clear input (CLR),
Preset input (PRE)

Question
No: 10 ( Marks: 1 )  Please choose one
In
asynchronous transmission when the transmission line is idle, _________
► It is set to logic
low
► It is set to logic
high (Page 356)
► Remains in previous
state
► State of transmission
line is not used to start transmission
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