CS302 Final Term Solved Past Papers By Moaaz

 CS302 Final Term Solved MCQS By Moaz

Question No: 1 ( Marks: 1 ) - Please choose one A 8-bit serial in / parallel out shift register contains the value “8”, _____ clock signal(s) will be required to shift the value completely out of the register. ► 1 ► 2 ► 4 ► 8 (Page 356) Question No: 2 ( Marks: 1 ) - Please choose one  In a sequential circuit the next state is determined by ________ and _______ ► State variable, current state ► Current state, flip-flop output ► Current state and external input (Page 318) ► Input and clock signal applied Question No: 3 ( Marks: 1 ) - Please choose one The divide-by-60 counter in digital clock is implemented by using two cascading counters: ► Mod-6, Mod-10 (Page 299) ► Mod-50, Mod-10 ► Mod-10, Mod-50 ► Mod-50, Mod-6 Question No: 4 ( Marks: 1 ) - Please choose one In NOR gate based S-R latch if both S and R inputs are set to logic 0, the previous output state is maintained. ► True (Page 221) ► False

Question No: 5 ( Marks: 1 ) - Please choose one The minimum time for which the input signal has to be maintained at the input of flip-flop is called ______ of the flip-flop. ► Set-up time ► Hold time (Page 242) ► Pulse Interval time ► Pulse Stability time (PST) Question No: 6 ( Marks: 1 ) - Please choose one 74HC163 has two enable input pins which are _______ and _________ ► ENP, ENT (Page 285) ► ENI, ENC ► ENP, ENC ► ENT, ENI

Question No: 7 ( Marks: 1 ) - Please choose one ____________ is said to occur when multiple internal variables change due to change in one input variable ► Clock Skew ► Race condition (Page 267) ► Hold delay ► Hold and Wait

Question No: 8 ( Marks: 1 ) - Please choose one The_____________ input overrides the ________ input ► Asynchronous, synchronous (Page 369) ► Synchronous, asynchronous ► Preset input (PRE), Clear input (CLR) ► Clear input (CLR), Preset input (PRE) Question No: 9 ( Marks: 1 ) - Please choose one A decade counter is __________. ► Mod-3 counter ► Mod-5 counter ► Mod-8 counter ► Mod-10 counter (Page 274)

Question No: 10 ( Marks: 1 ) - Please choose one In asynchronous transmission when the transmission line is idle, _________ ► It is set to logic low ► It is set to logic high (Page 356) ► Remains in previous state ► State of transmission line is not used to start transmission Download Complete CS302 Final Term Solution File By Moaz Click On Link Given Below https://drive.google.com/open?id=1lj7XTulIUI4Pum9-n-kLRRtZWZIygaUa